The present inventive concept relates to signal processing, and more particularly to a frequency divider and a phase locked loop (PLL) including the frequency divider.
A frequency divider generates an output signal by dividing an input signal such that a frequency of the output signal is lower than a frequency of the input signal. The frequency divider may be employed in a clock generator, such as a phase locked loop (PLL), or a frequency synthesizer, and various integrated circuits including the clock generator. The frequency divider may be categorized into an odd number frequency divider and an even number frequency divider depending on a division ratio of the frequency divider.